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Abstract |
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This lecture targets the embedded system developer, tools engineer, and researcher who needs to understand the current problems, current solutions, and future trends, in creating real-time systems. The viewer is introduced to the real-time dichotomy between the tools for hardware design and software design.
Hardware description languages, such as VHDL, already represent events on a time scale suitable for designing synchronous digital logic. Unfortunately, new software tools are still needed to support this same level of real-time determinism. Embedded software developers today typically use a C compiler to build programs that sequentially convert a finite series of bits into another finite series of bits – i.e. software programs without built-in knowledge of execution time and the underlying hardware.
Dr. Lee introduces the viewing audience to his Ptolemy II research tool that offers several potential solutions based on time, precedence ordering, causality, and synchronization with a focus on a new computational theory called “The Tagged Signal Model”. Most of the new software components presented are data driven abstractions called actors, rather than designs handicapped by threads, processes, objects, and other sequentially executed procedures used by most embedded software developers today.
Watch the lecture now by clicking on the "watch lecture" or "review transcript" links...
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Title |
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Building Unreliable Systems out of Reliable Components:
The Real-Time Story |
| Author |
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Dr. Edward Lee |
Sponsors |
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UC Berkeley's EECS Department; Santa Clara Valley Chapter of the IEEE Computer Society; Shannon Lecture Series; Embedded Components, Inc. |
Copyright |
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2005 |
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Ptolemy II (UC Berkeley real-time component research tool developed by Dr. Lee) created from a set of Java packages supporting heterogeneous modeling, simulation, and design of concurrent systems; Simulink® (The Mathworks platform) for multidomain simulation and Model-Based Design for dynamic systems; TinyOS (open-source operating system) designed for wireless embedded sensor networks; nesC (an open-source compiler) for a new language based on C designed to support the TinyOS project; SCADE (by Esterel Technologies) the standard design tool used extensively by avionics market leaders for the production of safety- and business-critical embedded software |
Components
Discussed |
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LXI IEEE-1588 demonstration kits; Ethernet; RTOS: Priority-based Preemptive; Actors; Objects; Procedures |
Services
Discussed |
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Dr. Lee's research and related benefits such as PhD theses development and real-time consulting |
Key Words and Phrases |
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Abstract Semantics, Actor Oriented Design, Actors, Ada, Alberto Sangiovanni-Vincentelli, Assembler, Automotive Control Software, Avionics Control Software, Behaviors, Bench Testing, Berkeley EECS Annual Research Symposium (BEARS), Brian Selic, Burt Sutherland, C compiler, C++ Compiler, Caches, CDC 6600 Computer, Chess Center, Click, Communicating Sequential Processes, Computation, Concurrency, Continuous Time Models, Control System Design, Control Theory, CPU, CSP, Debuggers, Deep Pipelines, Design Methodology, Digital Signal Processor, Discrete Event Models, Discrete Time Models, Distributed Computation, DSP, Dynamic Dataflow Models, Dynamic Dispatch, Eddie Kohler, Edward Lee, Embedded Software, Esterel Technologies, Ethernet, FlexRay, Garbage Collection, Hybrid Systems, Hybrid Systems Modeling, IEEE 1588, In-curcuit Emulator, Instruction Set Simulator, Interrupt, Interrupt Service Routine, Ivan Sutherland, Java, Java Virtual Machine, JIT, Just-In-Time Compilation, LabView, Lustre, Memory Hierarchy, Memory Management, Microprocessor, MIT's Lincoln TX-2 Group, Model-Based Design, Moore’s Law, Multilevel Caches, Multitasking, nesC, Networked Platforms, Networking, ns-2, Object Oriented Design, Objects, Operating System, OPNET, Pipelines, PN, Ports, Power Management, Procedures, Process Networks, Processes, Programming Languages, Ptolemy, Ptolemy II, Real-Time, Real-Time Object Oriented Modeling, Real-Time Operating Systems, Real-Time UML, Reliable Systems, ROOM, RTOS, Safety Critical Systems, SCADE, Schedulability, Schedulability Analysis, Scoreboarding, SDF, Sequential Processes, Simulink, Sketchpad, Smalltalk, Speculative Execution, Statistical Speedup Techniques, Synchronous Dataflow, Synchronous Digital Logic, Tagged Signal Model, TCP, The MathWorks, Theory Of Complexity, Theory of Hybrid Systems, Threads, Time Triggered Architectures, Timing, TinyOS, Transmission Control Protocol, TTA, TX-2 Computer, UC Berkeley's Computer Sciences Department, UC Berkeley's Electrical Engineering Department, UML, UML 2.0, Unified Modeling Language, Validation, Very High Speed Integrated Circuit (VHSIC) Hardware Description Language, VHDL, Virtual Memory, Wind River, Worst-Case Execution Time, Zeno Systems |
| Formats |
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| Status |
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Approved for publicaiton: 2/15/06 |
| Length |
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35 slides, 65 minutes of audio |
ECI Product ID |
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ECI20051117001 |
| Shipping Weight |
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N/A |
| Price |
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*free |
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